Superconducting qubits

Superconducting qubits are quantum bits built from lithographically patterned superconducting circuits in which a Josephson junction provides the nonlinearity that turns a resonator into a controllable two-level system. They are the modality behind several leading processors, offering nanosecond-to-microsecond gate speeds at the cost of coherence times measured in tens to hundreds of microseconds.

#How they work

A Josephson junction is a thin insulating barrier between two superconductors that carries a lossless supercurrent and behaves as a nonlinear inductor. Combined with a capacitor, it forms an anharmonic oscillator whose two lowest energy levels serve as the Qubit states 0 and 1. The anharmonicity is essential: it makes the 0-to-1 transition a different frequency from higher transitions, so a microwave pulse can drive one transition without leaking population into other levels. Gates are performed by shaped microwave pulses (single-qubit rotations) and by tunable couplings or resonators (two-qubit gates), all at gigahertz frequencies.

The dominant design is the transmon, introduced in 2007, which shunts the junction with a large capacitor to suppress sensitivity to charge noise (Koch et al. 2007). Trading some anharmonicity for much longer coherence, the transmon became the workhorse of the field and underlies most current superconducting processors (Krantz et al. 2019).

#Cryogenics and control

Because the qubit energy splitting corresponds to a temperature far below 1 kelvin, the circuits must be cooled in a dilution refrigerator to roughly 10 to 20 millikelvin so that thermal photons do not randomly excite them. Each qubit needs its own microwave control and readout lines, so wiring density and the heat load of coaxial cabling become serious engineering constraints as chips grow. Readout is typically dispersive: the qubit state shifts the frequency of a coupled resonator, which is probed with a low-power microwave tone.

#Coherence and decoherence

The central weakness is Decoherence. Superconducting qubits couple to many noise sources, including two-level defects in oxide interfaces, quasiparticles, flux noise, and stray photons, which limit energy-relaxation and dephasing times to roughly tens to a few hundred microseconds as of early 2026. Gates are fast relative to these times, giving thousands of operations before a qubit decoheres, but that is still far short of the near-perfect operations a cryptanalytic computation would require. Closing this gap is the purpose of Quantum error correction, which encodes one Logical qubit across many physical qubits.

#Who uses them

• IBM Quantum builds transmon processors such as the Heron and Condor families and publishes a roadmap toward a fault-tolerant machine (IBM roadmap).
• Google Quantum AI demonstrated below-threshold error correction on its 105-qubit Willow chip in 2024 (Google 2024).
• Rigetti Computing designs and fabricates its own multi-chip superconducting processors.

#Strengths and limitations

Strengths include fast gates, compatibility with established semiconductor fabrication, and rapid design iteration on solid-state chips. Limitations include short coherence relative to trapped ions, the need for millikelvin cryogenics, dense microwave wiring that complicates scaling, and manufacturing variation that leaves qubits with slightly different frequencies. No single modality has won; superconducting circuits compete with Trapped-ion qubits, Neutral-atom qubits, and Photonic quantum computing on different axes of speed, fidelity, and scalability.

#Relevance to cryptography

Superconducting processors are the platform on which most public error-correction milestones have been reached, but they remain in the NISQ era, with no demonstrated advantage on any cryptographically meaningful task. Running Shor's algorithm at scale would require millions of high-quality physical qubits sustained fault-tolerantly, far beyond current devices, which is why the timing of Q-Day remains uncertain.